1. Field of the Invention
The present invention relates to a chip package, and in particular relates to a sealing ring structure of a chip package.
2. Description of the Related Art
Wafer level packaging technology has been developed for packaging chips. After a wafer level package is completed, a cutting process is performed between each chip to separate the chips from each other. In order to reduce the probability of cracks, produced by the cutting process, extending to the inner side portions of the chip, a sealing ring is disposed between each chip to enhance chip package reliability. However, because the sealing ring occupies an extra area of a wafer, the amount of dies formed on the wafer is reduced.